1. Field of the Invention
The present invention relates to a semiconductor memory having sense amplifiers.
2. Description of the Related Art
FIG. 1 shows a conventional DRAM memory core. The memory core is provided with four memory blocks BLK0-3. Each memory block BLK has two memory cell arrays ALY and a sense amplifier array RSA (RSA0-3) to be shared between these memory cell arrays ALY. The sense amplifier array RSA consists of, for example, 1024 sense amplifiers (not shown) which are arranged in the horizontal direction of the diagram.
The memory cell arrays ALY have a plurality of memory cells MC to be selected by word lines WL and bit lines BL (or /BL). The sense amplifier arrays RSA each have signal lines of first activating signals PSA (PSA0-3) and NSA (NSA0-3), a second activating signal /RCL (/RCL0-3), and a third activating signal WCL (WCL0-3) which are laid in the horizontal direction of the diagram. In the following description, the symbols of the signals (such as PSA, NSA, /RCL, and WCL) will be also used as symbols for the signal lines that transmit the respective signals.
The memory core also includes first sense amplifier control circuits C1 (C1-0, C1-1, C1-2, C1-3) and second sense amplifier control circuits C2 (C2-0, C2-1, C2-2, C2-3) corresponding to the respective sense amplifier arrays RSA, row decoders RDEC corresponding to the respective memory cell arrays ALY, and a column decoder CDEC.
The first sense amplifier control circuits C1 activate the first activating signals PSA (PSA0-3) and NSA (NSA0-3) in accordance with an upper row address R1, R0. The activation of the first activating signals PSA and NSA activates latches (to be described later) of all the sense amplifiers in the corresponding sense amplifier arrays RSA. The second sense amplifier control circuits C2 activate the second activating signals /RCL and the third activating signals WCL in accordance with the upper row address R1, R0.
The row decoders RDEC operate in accordance with a 3-bit row address RADD including the upper row address R1, R0, and select the word lines WL in accordance with a lower row address RADD. The column decoder CDEC activates column selecting signals CL (CL0, 1, . . . ) in accordance with a column address CADD. The column selecting signals CL are signals common to the four memory blocks BLK0-3. The activation of the column selecting signals CL turns on predetermined column switches (to be described later) of sense amplifier arrays RSA that are activated by the first activating signals PSA and NSA. That is, the sense amplifiers are selected in accordance with the column selecting signals CL.
FIG. 2 shows the details of the sense amplifier array RSA0 of FIG. 1. The sense amplifier arrays RSA1-3 have the same structure as that of the sense amplifier array RSA0. FIG. 2 is rotated 90xc2x0 relative to FIG. 1.
The sense amplifier array RSA0 has a plurality of sense amplifiers SA corresponding to the respective bit line pairs BL, /BL. Isolation gates for isolating the sense amplifiers SA from the memory cell arrays ALY are formed on both sides of the sense amplifiers SA (right and left in the diagram). The isolation gates are controlled by bit line selecting signals /SBTL and /SBTR, respectively. That is, the sense amplifier array RSA0 is shared between the memory cell arrays ALY on both sides by means of the bit line selecting signals /SBTL and /SBTR.
Each sense amplifier includes a latch 2, a read control circuit 4, and a write control circuit 6. The latch 2 is composed of two CMOS inverters having inputs and outputs connected to each other. When the first activating signals PSA0 and NSA0 are activated (high level and low level, respectively), the latch 2 is activated to amplify data on the bit line BL (or /BL) and latch the data amplified. The first activating signal lines PSA0 and NSA0 are laid common to all the sense amplifiers SA in the sense amplifier array RSA0. On this account, the first activating signal lines PSA0 and NSA0 have a great wiring length and high load capacitance. In read operations and write operations, the activation of the first activating signals PSA0 and NSA0 activates all the latches 2 in the sense amplifier array RSA0 simultaneously.
The read control circuit 4 has an amplifying transistor 4a and a switching transistor 4b (column switch) for each bit line BL, /BL. Each amplifying transistor 4a is connected at its gate to the bit line BL (or /BL) and at its source to the second activating signal line /RCL0. Each switching transistor 4b is connected at its source to the drain of an amplifying transistor 4a, at its gate to the column selecting signal line CL, and at its drain to a read data bus line RDB0 (or /RDB0). The second activating signal line /RCL0 is laid common to the amplifying transistors 4a of all the sense amplifiers SA in the sense amplifier array RSA0. On this account, the second activating signal line /RCL0 has a great wiring length and high load capacitance.
The amplifying transistors 4a have the function of amplifying read data received at their gates and outputting the resultant to their drains. Such a circuit system of sense amplifiers in which the gates are connected to bit lines is generally referred to as direct sense system. In the direct sense system, the bit lines BL and /BL are not directly connected to the read data bus lines RDB0 and /RDB0. Therefore, even if the column selecting signal CL is activated before data read from the memory cells MC is amplified completely, the read operation will be performed properly without corruption of data on the bit lines BL and /BL. That is, it is suited to high-speed operation.
The write control circuit 6 has two switching transistors 6a and 6b in series for each bit line BL, /BL. Each switching transistor 6a is connected at one end to a write data bus line WDB0 (or /WDB). Each switching transistor 6b (column switch) is connected at one end to the bit line BL (or /BL). The two gates of the switching transistors 6a and 6b are connected to the third activating signal line WCL0 and the column selecting signal line CL (CL0-1), respectively. The third activating signal line WCL0 is laid common to the switching transistors 6a of all the sense amplifiers SA in the sense amplifier array RSA0. On this account, the third activating signal line WCL0 has a great wiring length and high load capacitance.
FIG. 3 shows the operations of the DRAM described above. In this example, the DRAM receives an active command ACTV from the exterior when in a standby state STBY, and then receives a read command READ and a write command WRITE to perform a read operation and a write operation in succession. After the write operation, the DRAM also receives a precharging command PRE from the exterior and precharges (equalizes) bit line pairs BL, /BL.
Initially, the active command ACTV and a row address RADD are supplied. A bit line resetting signal /BRS of the memory block BLK corresponding to the row address RADD turns to low level, releasing the precharge of the bit line pairs BL, /BL (FIG. 3(a)). The row decoder RDEC of FIG. 1 activates a word line WL in accordance with the row address RADD (FIG. 3(b)). Due to the activation of the word line WL, data is read from the memory cells MC to the bit lines BL (or /BL) (FIG. 3(c)).
Next, the first sense amplifier control circuit C1 corresponding to the row address RADD activates the first activating signals PSA and NSA (FIG. 3(d)). The first activating signal lines PSA and NSA are connected to the latches of all the sense amplifiers SA in the memory block BLK. Therefore, due to the activation of the first activating signal lines PSA and NSA, all the latches 2 in the memory block BLK start an amplifying operation, amplifying the voltage differences between the bit lines BL and /BL (FIG. 3(e)). All the latches 2 in the memory block BLK also latch the data amplified.
Now, the second sense amplifier control circuit C2 corresponding to the row address RADD activates the second activating signal /RCL and the third activating signal WCL (FIG. 3(f)). The activation of the second activating signal line /RCL supplies a source voltage to the amplifying transistors 4a in the read control circuits 4 of FIG. 2, so that the amplifying transistors 4a start operating. The activation of the third activating signal WCL turns on the switching transistors 6a in the write control circuits 6 of FIG. 2. Here, since no column selecting signal CL is activated yet, the bit lines BL and /BL are not connected to the write data bus lines WDB and /WDB.
As shown in FIG. 1, the second activating signal line /RCL and the third activating signal line WCL are shared among all the sense amplifiers SA in the memory block BLK, and thus are great in wiring length and high in loads such as wiring capacitance. As a result, the second activating signal line /RCL and the third activating signal line WCL dull in waveform and become longer in transmission time. For this reason, the second activating signal /RCL and the third activating signal WCL are activated without waiting for the read command READ or the write command WRITE. For example, if the second activating signal /RCL were changed after the reception of the read command READ, the read control circuits 4 might be late in starting operation with a longer read cycle. The same holds true for the write control circuits 6.
After the data on the bit lines BL (or /BL) is amplified, the read command READ and a column address CADD are supplied. The column decoder CDEC of FIG. 1 activates any one of the column selecting signals CL in accordance with the column address CADD (FIG. 3(g)). The activation of the column selecting signal CL turns on the switching transistors 4b of FIG. 2, whereby the complementary read data amplified by the amplifying transistors 4a is transmitted to the read data bus lines RDB and /RDB. Subsequently, an amplifier AMP of FIG. 1 amplifies and outputs the read data to the exterior.
Next, the write command WRITE, a column address CADD, and write data are supplied. Here, the word line WL and the sense amplifiers SA are kept activated. The write data is amplified by the amplifier AMP of FIG. 1 and transmitted as complementary write data to the write data bus WDB, /WDB. The column decoder CDEC activates any one of the column selecting signals CL in accordance with the column address CADD (FIG. 3(h)). The activation of the column selecting signal CL turns on the switching transistors 6b in the write control circuit 6 of FIG. 2, thereby connecting the write data bus lines WDB, /WDB and the bit lines BL, /BL, respectively. The write data is transmitted to the bit lines BL and /BL and written to memory cells MC (FIG. 3(i)).
Then, the precharging command PRE is supplied. The precharging command PRE inactivates the word line WL, the first activating signals PSA and NSA, the second activating signal /RCL, and the third activating signal WCL (FIGS. 3(j), (k), (l)). In addition, the bit line resetting signal /BRS is activated (FIG. 3(m)) and the bit line pairs BL, /BL are precharged (FIG. 3(n)).
In the conventional direct sense system, the second and third activating signal lines /RCL and WCL were connected to all the sense amplifiers SA in the sense amplifier arrays RSA as described above, with great wiring lengths and high load capacitance. Therefore, to obtain desired read cycle time and write cycle time, the second sense amplifier control circuits C2 had to start operation in synchronization with the active command ACTV. More specifically, the amplifying transistors 4a of the read control circuits 4 and the switching transistors 6a of the write control circuits 6 had to be operated before the supply of the read command READ and the write command WRITE. This consequently required, for example, that the write control circuits 6 be operated even in read operations. The operation of circuits extraneous to original operation consumed extra power.
Moreover, the read control circuits 4 and the write control circuits 6 required high driving capacity since they needed to drive the second and third activating signal lines /RCL and WCL which were great in wiring length and high in loads. This meant a problem of greater power consumption in read operations and write operations. Furthermore, there has been a problem of high peak current due to the simultaneous operation of the read control circuits 4 and the write control circuits 6 which required high driving capacity.
An object of the present invention is to reduce power consumption of a semiconductor memory. In particular, the reduction of power consumption is intended for a semiconductor memory that has sense amplifiers of a direct sense system.
Another object of the present invention is to perform read operations and write operations of a semiconductor memory at high speed.
According to one of the aspects of the semiconductor memory of the present invention, a memory cell array has a plurality of memory cells and a plurality of bit lines for transmitting data to these memory cells, respectively. A plurality of sense amplifiers is formed corresponding to the bit lines, respectively. The sense amplifiers each include a latch, an amplifying transistor, and a column switch. The sense amplifier arrays are formed corresponding to the memory cell array. Predetermined numbers of sense amplifiers make a plurality of sense amplifier arrays.
The latch amplifies and holds data on a bit line in response to the activation of a first activating signal. The amplifying transistor amplifies a voltage level of the bit line received at a gate of the amplifying transistor upon receiving the activation of a second activating signal at a source of the amplifying transistor. The column switch connects the drain of the amplifying transistor to a read data bus line in response to the activation of a column selecting signal.
A first sense amplifier control circuit generates the first activating signal. The first activating signal is supplied to all the sense amplifiers simultaneously. That is, the latches of all the sense amplifiers are simultaneously activated to amplify the data on the bit lines. A plurality of second sense amplifier control circuits generates the second activating signals having different activating timings from each other, respectively. The second activating signals are supplied to different sense amplifiers, respectively. That is, the amplifying transistors of the sense amplifiers are activated in units of sense amplifier arrays. In other words, the number of sense amplifier arrays and the number of amplifying transistors to be operated at a time are set in accordance with the number of signal lines of second activating signals.
Since the number of amplifying transistors to be operated decreases, power consumption is reduced in read operations. In addition, because the amplifying transistors are activated in units of sense amplifier arrays in response to the plurality of second activating signals, the wiring length of signal lines for transmitting the second activating signals can be made shorter than the wiring length in conventional art. The signal lines become smaller in loads such as load capacitance and wiring resistance. Therefore, buffer circuits of the second sense amplifier control circuits that generate the second activating signals can be lowered in driving capacity. As a result, power consumption of the sense amplifiers can be reduced significantly in read operations.
Having smaller loads in the aforementioned signal lines can decrease the transmission time of the second activating signals, with a reduction in read operation time. As stated above, all the latches are simultaneously activated to amplify the data on the bit lines. That is, it is possible for each of the sense amplifiers to have the data read from the memory cells amplified by their respective latches in advance. Therefore, a large amount of data can be consecutively output to the exterior at high speed by simply activating the second activating signals in succession.
According to another aspect of the semiconductor memory of the present invention, word lines control connection between storage nodes of the memory cells and the bit lines. An address input circuit receives a row address for selecting one of the word lines and a column address for selecting one of the column switches. The first sense amplifier control circuit activates the first activating signal in accordance with the row address. The second sense amplifier control circuits activate the second activating signals in accordance with the row address and the column address, respectively. Here, the row address and the column address may be supplied from the exterior in time division or simultaneously.
As described above, the number of sense amplifier arrays which operate simultaneously is set in accordance with the number of second activating signals. Since the sense amplifiers are respectively connected to the bit lines, the sense amplifier arrays are lined in the direction orthogonal to the direction that the bit lines are lined (the direction the sense amplifiers are lined in). Therefore, when the logic of the column address is included in the second activating signals, the predetermined number of sense amplifiers connected to the bit lines of the memory cell array can be easily divided into a plurality of sense amplifier arrays. On the contrary, when the plurality of second activating signals are generated from the row address alone, the sense amplifier arrays should be lined in the direction orthogonal to the direction that the word lines are lined. However, making such division is impossible since the sense amplifiers are lined along the direction the word lines run.
According to another aspect of the semiconductor memory of the present invention, a plurality of memory blocks to be selected in accordance with the row address, respectively, are formed. The memory blocks each have the memory cell array and a plurality of the sense amplifier arrays arranged in a first direction along the memory cell array. Even when the plurality of memory blocks is formed, power consumption of the sense amplifiers can be reduced significantly in read operations as described above.
According to another aspect of the semiconductor memory of the present invention, the memory blocks are arranged in a second direction orthogonal to the first direction. The first sense amplifier control circuit is arranged at one end of each of the respective memory blocks along the second direction. The second sense amplifier control circuits are arranged outside the memory blocks corresponding to the sense amplifier arrays along the first direction.
Since the direction the second sense amplifier control circuits are arranged in and the direction the sense amplifier arrays are arranged in are both the same first direction, the signal lines of the second activating signals can be minimized in wiring length. Besides, for all the sense amplifier arrays, the second activating signal lines can be made equal in wiring lengths. This allows a further reduction in the transmission time of the second activating signals.
According to another aspect of the semiconductor memory of the present invention, second activating signal lines for transmitting the second activating signals to the sense amplifiers are laid in a first wiring layer, in which signal lines of the column selecting signals are laid. For transmitting the column selecting signals in a small amount of time, the signal lines for transmitting the column selecting signals are typically laid in a wiring layer of low resistance. For this reason, the transmission time of the second activating signals can be further reduced.
According to another aspect of the semiconductor memory of the present invention, the sense amplifier arrays are arranged in the first direction along the memory cell array. The second activating signal lines for transmitting the second activating signals to the sense amplifiers are laid in the second direction in the first wiring layer, in which signal lines of the column selecting signals are laid, the second activating signal lines are laid as far as the sense amplifier arrays. Moreover, within the sense amplifier arrays, the second activating signal lines are laid in the first direction in a second wiring layer, in which the first activating signal line(s) for transmitting the first activating signal(s) are laid. Since the relatively long wiring up to the sense amplifier arrays is formed in the first wiring layer of low resistance, it is possible to lower the total wiring resistance of the second activating signal lines. This allows reduction in the transmission time of the second activating signals.
According to another aspect of the semiconductor memory of the present invention, a plurality of third sense amplifier control circuits generates third activating signals having different activating timings from each other, respectively. The sense amplifiers each include a switch and a column switch. The switch turns on in response to any one of the third activating signals to transmit the data on the bit line. The column switch connects corresponding one of the bit lines to a write data bus line through the switch in response to the activation of the column selecting signal.
The plurality of third activating signals are supplied to the plurality of sense amplifier arrays, respectively, each includes a predetermined number of sense amplifiers. That is, the switches of the sense amplifiers are activated in units of sense amplifier arrays. Since the number of switches to be operated decreases, power consumption is reduced in write operations. In addition, since the switches are activated in units of sense amplifier arrays in response to the plurality of third activating signals, the wiring length of signal lines for transmitting the third activating signals can be made shorter than the wiring length in conventional art. The signal lines become smaller in loads such as load capacitance and wiring resistance. Therefore, buffer circuits of the third sense amplifier control circuits that generate the third activating signals can be lowered in driving capacity. As a result, power consumption of the sense amplifiers can be reduced significantly in write operations. The shorter transmission time of the third activating signals allows reduction in write operation time.
For example, like the second activating signal lines described above, third activating signal lines for transmitting the third activating signals can be laid in the first wiring layer, in which the signal lines of the column selecting signals are laid, with a further reduction in the transmission time of the third activating signals.
According to another aspect of the semiconductor memory of the present invention, the second sense amplifier control circuits generate the second activating signals in read operations. The third sense amplifier control circuits generate the third activating signals in write operations. Since the read operations and the write operations involve only necessary control circuits, respectively, it is possible to reduce power consumption.